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Micrel
Overview of programming bit
Address
Data
MICRF506BML/YML
A6..A0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
D7
LNA_by
Modulation1
CP_HI
IFBias_s
(“1”)
Mod_F2
-
-
BitRate_clkS1
SC_HI
(“1”)
PrescalMode_s
(“0”)
-
-
N0_7
-
M0_7
-
-
N1_7
-
M1_7
Div2_HI
(“1”)
-
FEE_7
D6
PA2
Modulation0
SC_by
IFA_HG
(“1”)
Mod_F1
-
Mod_clkS2
BitRate_clkS0
ScClk_X2
(“1”)
Prescal_s
(“0”)
-
-
N0_6
-
M0_6
-
-
N1_6
-
M1_6
LO_IB1
(“0”)
-
FEE_6
D5
PA1
OL_opamp_en
(“0”)
VCO_by
(“0”)
VCO_BIAS_s
(“0”)
Mod_F0
Mod_FHG
(“0”)
Mod_clkS1
RefClk_K5
ScSW_en
(“0”)
XCOAR_en
(”1”)
A0_5
-
N0_5
-
M0_5
A1_5
-
N1_5
-
M1_5
LO_IB0
(“1”)
-
FEE_5
D4
PA0
PA_LDc_en
(”0”)
PA_by
VCO_IB2
Mod_I4
Mod_shape
(“1”)
Mod_clkS0
RefClk_K4
ScClk4
XCOtune4
A0_4
-
N0_4
-
M0_4
A1_4
-
N1_4
-
M1_4
PA_IB4
(”0”)
-
FEE_4
D3
Sync_en
RSSI_en
OUTS3
VCO_IB1
Mod_I3
Mod_A3
BitSync_clkS2
RefClk_K3
ScClk3
XCOtune3
A0_3
N0_11
N0_3
M0_11
M0_3
A1_3
N1_11
N1_3
M1_11
M1_3
PA_IB3
(”0”)
FEEC_3
FEE_3
D2
Mode1
LD_en
OUTS2
VCO_IB0
Mod_I2
Mod_A2
BitSync_clkS1
RefClk_K2
ScClk2
XCOtune2
A0_2
N0_10
N0_2
M0_10
M0_2
A1_2
N1_10
N1_2
M1_10
M1_2
PA_IB2
(”0”)
FEEC_2
FEE_2
D1
Mode0
PF_FC1
OUTS1
VCO_freq1
Mod_I1
Mod_A1
BitSync_clkS0
RefClk_K1
ScClk1
XCOtune1
A0_1
N0_9
N0_1
M0_9
M0_1
A1_1
N1_9
N1_1
M1_9
M1_1
PA_IB1
(”1”)
FEEC_1
FEE_1
D0
Load_en
PF_FC0
OUTS0
VCO_freq0
Mod_I0
Mod_A0
BitRate_clkS2
RefClk_K0
ScClk0
XCOtune0
A0_0
N0_8
N0_0
M0_8
M0_0
A1_0
N1_8
N1_0
M1_8
M1_0
PA_IB0
(“1”)
FEEC_0
FEE_0
Table 1: Detailed description of programming bit
ADR #
0000000
0000001
BIT #
7
6
5
4
3
2
1
0
7
6
5
NAME
By_LNA
PA2
PA1
PA0
Sync_en
Mode1
Mode0
Load_en
Modulation1
Modulation0
OL_opamp_en
DESCRIPTION
LNA bypass on/off
Power amplifier level, 3.bit
Power amplifier level, 2.bit
Power amplifier level, 1.bit
Synchronizer Mode bit
Main Mode selection 2. Bit
Main Mode selection 1. Bit
Load generation (1=enable)
Modulation selection 2.bit
Modulation selection 1.bit
“0” mandatory. Opamp in OpenLoop circuit (0=disable)
COMMENTS
Ref. Table 6
Ref. Table 6
Ref. Table 6
Ref. Table 3
Ref. Table 2
Ref. Table 2
Ref. Table 4
Ref. Table 4
“0” mandatory. PA controlled by Lock Detect
July 2006
4
3
PA_LDc_en
RSSI_en
(0=disable)
RSSI function (1=enable)
35
Ref. Table 6
M9999-092904
+1 408-944-0800
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